System ESD Protection Design Addressing PCB And IC Aspects
March 14-15, 2018 • 9:00 AM – 6:00 PM
Instructors: Jeffrey Dunnihoo, Pragma Design; Harald Gossner, Intel Deutschland GmBH
An effective and cost efficient protection of electronic system against ESD stress pulses specified by IEC 61000-4-2 is paramount for any system design. The tutorial is a hands-on training course for performing a simulation based optimization of PCB ESD protection design and provides deep understanding of the relevant performance criteria both of TVS diodes and IO circuit. This tutorial presents the collective knowledge of system designers and system testing experts and state-of-the-art techniques for achieving efficient system-level ESD protection, with minimum impact on the system performance. All categories of system failures ranging from ‘hard’ to ‘soft’ types are considered to review simulation and tool applications that can be used.
By examining the ESD Industry Council’s “SEED” (System Efficient ESD Design) approach as recommended by Industry Council on Target Levels and JEDEC (JEP172), the tutorial will establish the importance of co-design efforts from both IC supplier and system builder perspectives. ESD designers often face challenges in meeting customers’ system-level ESD requirements and, therefore, a clear understanding of the techniques presented here will facilitate effective simulation approaches leading to better solutions without compromising system performance.
The method allows to achieve first time right PCB builts and reduces the respin effort for boards and ICs. Based on a TLP characterization of SoC interface circuits and TVS diodes, simulation models for impedance and clamping behavior as well as failure threshold are extracted. These are used to assess design solutions by transient simulations. This is showcased by real world examples.
In addition to SEED simulation “First Time Right” design methodologies, the course will review advanced lab analysis and characterization techniques (and limitations), including current reconstruction scanning, susceptibility scanning, resonance scanning, and embedded ESD detector techologies and tools. With the authors of the comprehensive textbook on the subject “System Level ESD Co-Design”, Mr. Dunnihoo and Mr. Gossner will discuss hands-on experience and in-depth knowledge in topics ranging from ESD design and the physics of system ESD phenomena to tools and techniques to address soft failures and strategies to design ESD-robust systems that include mobile and automotive applications.
March 16, 2018
Instructors: Horst A. Gieser and Heinrich Wolf, Fraunhofer EMFT
Advanced ESD Characterization
How to gain accurate insight in the electrical behavior of protection elements and of elements to be protected. The seminar covers the following topics: Accuracy aspects of transmission line testing, characterization and parameter extraction from DC to very fast transmission line pulsing including electro thermal aspects, how to choose the failure criteria (leakage and RF-degradation), how to gain accurate transient device behavior applying repetitive ps-pulsing, high bandwidth system level measurements applying a current sensor.
ESD Failure Reproduction and Alternative Models
How to look at a failure and how to reproduce it. CDM-Pitfalls; Capacitively Coupled TLP; Cable Discharge; Charged Board Model; ESD from Outside – straight through passivation ESD on LEDs.
Learn to know your structures in the ATIS test lab and discuss the results with the speakers and your colleagues. Learn to know characterization equipment and methods.
Please contact firstname.lastname@example.org to discuss your individual test wishes at least before March 1st, 2018 and send some devices to be tested during a demonstration at the workshop. The speakers reserve the right to prioritize projects in view of interest to the audience.